Without limiting the scope of the invention, its background is described in connection with, bipolar transistors as an example.
Heretofore, in this field, GaAs/AlGaAs heterojunction bipolar transistors (HBT) have been fabricated using mesa technology in which the collector, base and emitter epi layers are subsequently grown during a single epitaxial deposition run. The emitter and base epi layer are selectively removed using two etch steps for making contact to the base and collector areas, respectively. These etches result in steps in the GaAs ranging in height between 0.4 and 2.0 microns for a typical mesa HBTs. Although high quality HBTs can be fabricated in this manner, the resulting mesa structure results in very severe topography making it difficult to incorporate a multilevel metal system as required for high levels of integration.
Planar heterojunction bipolar transistors have been fabricated as elements of integrated circuits in the emitter down configuration (See U.S. Pat. No. 4,573,064). This avoids the mesa topography but this technology requires all of the NPN transistors to be connected in the common emitter configuration which severely limits its applications for analog/linear ICs.
Although a single epitaxial deposition run as used in the foregoing mesa HBTs and emitter-down HBTs does simplify the fabrication process, it limits the types of structures which can be integrated together on a single chip.
An alternative has been to grow an emitter epilayer onto an implanted base with Zn as the base dopant because of the high mass and low implant range. However, implanted Zn is difficult to activate at low temperatures. Raising the temperature high enough for good activation results in excessive diffusion due m the large diffusion coefficient for Zn, significantly increasing the base width and lateral dimensions and degrading the frequency response. Additionally, this process integrates only a single type of device, the NPN HBT.
Improved performance as well as increased circuit flexibility has been made possible by integrating both NPN and PNP bipolar transistors on the same chip. Silicon digital circuits make use of vertical NPN switching transistors and PNP transistors for input logic, current sources and level shifting. Silicon linear circuits are routinely using integrated NPN and PNP transistors for improved circuit performance.